Combinational Circuit
Q21.
A half Combinational Circuit is implemented with XOR and AND gates. A full Combinational Circuit is implemented with two half Combinational Circuits and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary Combinational Circuit is implemented by using four full Combinational Circuits. The total propagation time of this 4-bit binary Combinational Circuit in microseconds is____________.Q22.
Consider an eight-bit ripple-carry Combinational Circuit for computing the sum of A and B, where A and B are integers represented in 2's complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is ________.Q23.
How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates?Q24.
In a 8-bit ripple carry adder using identical full adders, each full adder takes 34 ns for computing sum. If the time taken for 8-bit addition is 90 ns, find time taken by each full adder to find carry.Q26.
The following circuit implements a two-input AND gate using two 2-1 multiplexers. What are the values of X_1, X_2, X_3?Q27.
The control signal functions of a 4-bit binary counter are given below (where X is "don't care"): Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence:Q29.
In a look-ahead carry generator, the carry generate function i G and the carry propagate function P_{i} for inputs A_{i} and B_{i} are given by: P_{i}=A_{i}\bigoplus B_{i} \; and \; G_{i}=A_{i}B_{i} The expressions for the sum bit S_{i} and the carry bit C_{i+1} of the look-ahead carry Combinational Circuit are given by: S_{i}=P_{i}\bigoplus C_{i} \; and \; C_{i+1}=G_{i}+P_{i}C_{i} Consider a two-level logic implementation of the look-ahead carry generator. Assume that all P_{i} and G_{i} are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit Combinational Circuit with and S_{3},S_{2},S_{1},S_{0} as C_{4} its outputs are respectively:Q30.
How many 3-to-8 line decoders with an enable input are needed to construct a 6- to-64 line decoder without using any other logic gates?