Combinational Circuit
Q31.
The boolean function for a combinational circuit with four inputs is represented by the following Karnaugh map.Which of the product terms given below is an essential prime implicant of the function?Q32.
The circuit shown below implements a 2-input NOR gate using two 2-4 MUX (control signal 1 selects the upper input). What are the values of signals x, y and z?Q33.
We consider addition of two 2's complement numbers b_{n-1}b_{n-2}...b_{0} and a_{n-1}a_{n-2}...a_{0}. A binary Combinational Circuit for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by c_{n-1}c_{n-2}...c_{0} and the carryout by c_{out} . Which one of the following options correctly identifies the overflow condition?Q34.
A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001,..., 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit \geq5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required?Q35.
Consider a multiplexer with X and Y as data inputs and Z as control input. Z = 0 selects input X, and Z = 1 selects input Y. What are the connections required to realize the 2-variable Boolean function f=T+R, without using any additional hardware?Q36.
A 4-bit carry look ahead Combinational Circuit, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the Combinational Circuit? Assume that the carry network has been implemented using two-level AND-OR logic.Q37.
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed?Q38.
Consider the ALU shown below If the operands are in 2's complement representation, which of the following operations can be performed by suitably setting the control lines K and C0 only (+ and - denote addition and subtraction respectively)?Q39.
Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier isQ40.
Consider the following circuit composed of XOR gates and non-inverting buffers The non-inverting buffers have delays \delta _{1}= 2ns and \delta _{2}= 4ns as shown in the figure. Both XOR gates and al wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0. If the following waveform is applied at input. A, how many transition (s) (change of logic levels) occur (s) at B during the interval from 0 to 10 ns?