GATE PYQ

Combinational Circuit

Q41.
Consider the following multiplexor where I0,I1,I2,I3 are four data input lines selected by two address line combinations A1A0 = 00,01,10,11 respectively and f is the output of the multiplexor. EN is the Enable input. The function f (x,y,z) implemented by the above circuit is

Q42.
The number of full and half-adders required to add 16-bit numbers is

Q43.
A multiplexer with a 4-bit data select input is a

Q44.
An N-bit carry lookahead adder, where N is a multiple of 4, employs ICs 74181 (4 bit ALU) and 74182 ( 4 bit carry lookahead generator). The minimum addition time using the best architecture for this adder is

Q45.
Consider the circuit in below figure which has a four bit binary number b_3b_2b_1b_0 as input and a five bit binary number, d_4d_3d_2d_1d_0 as output.

Q46.
Consider the circuit in figure. f implements

Q47.
Fig. below shows the circuit diagram of a wien bridge oscillator using an op-amp.The frequency of oscillation is given by f= 1/2 \pi CR. To have the system oscillate the ratio R_{2}/R_{1} should be

Q48.
The output F of the below multiplexer circuit can be represented by

Q49.
Consider the circuit shown below. The output of a 2:1 Mux is given by the function (ac' + bc). Which of the following is true?