Computer Organization
Q152.
A main memory unit with a capacity of 4 megabytes is built using 1Mx1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit isQ153.
A ROM is used to store the table for multiplication of two 8-bit unsigned integers. The size of ROM required isQ154.
The process of organizing the memory into two banks to allow 8-and 16-bit data operation is calledQ155.
Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: The advantages of CMOS technology over a MOS is:Q156.
The capacity of a memory unit is defined by the number of words multiplied by the number of bits/word. How many separate address and data lines are needed for a memory of 4K \times 16?Q158.
A computer which issues instructions in order, has only 2 registers and 3 opcodes ADD, SUB and MOV. Consider 2 different implementations of the following basic block :\begin{array}{l|l} \text { Case } 1 & \text { Case } 2 \\ \hline t 1=a+b ; & t 2=c+d \\ t 2=c+d ; & t 3=e-t 2 \\ t 3=e-t 2 ; & t 1=a+b \\ t 4=t 1-t 2 ; & t 4=t 1-t 2 \end{array}Assume that all operands are initially in memory. Final value of computation also has to reside in memory. Which one is better in terms of memory accesses and by how many MOV instructions?Q159.
Consider the given C-code and its corresponding assembly code, with a few operands U1-U4 being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable.Which one of the following options is a CORRECT replacement for operands in the position (U1, U2, U3, U4) in the above assembly code?Q160.
Consider the following instruction sequence where registers R_1,R_2 \text{ and }R_3 are general purpose and MEMORY[X] denotes the content at the memory location X.\begin{array}{llc} \textbf{Instruction} & \textbf{Semantics} & \textbf{Instruction Size} \text{ (bytes)} \\ \hline \text{MOV } R1, (5000) & R1 \leftarrow \text{MEMORY}[5000] & 4 \\ \hline \text{MOV } R2, (R3) & R2 \leftarrow \text{MEMORY}[R3] & 4 \\ \hline \text{ADD} R2, R1 & R2 \leftarrow R1 + R2 & 2 \\ \hline \text{MOV } (R3), R2 & \text{MEMORY}[R3] \leftarrow R2 & 4 \\ \hline \text{INC } R3 & R3 \leftarrow R3+1 & 2 \\ \hline \text{DEC } R1 & R1 \leftarrow R1-1 & 2 \\ \hline \text{BNZ } 1004 & \text{Branch if not zero to the} & 2 \\ & \text{given absolute address} \\ \hline \text{HALT} & \text{Stop} & 1 \\ \hline \end{array} Assume that the content of the memory location 5000 is 10, and the content of the register R_3 is 3000. The content of each of the memory locations from 3000 to 3020 is 50. The instruction sequence starts from the memory location 1000. All the numbers are in decimal format. Assume that the memory is byte addressable. After the execution of the program, the content of memory location 3010 is ____________