Computer Organization
Q171.
A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand field is _______ .Q172.
A byte addressable computer has a memory capacity of 2^{m} K B(k \text { bytes }) and can perform 2^{n} operations. An instruction involving 3 operands and one operator needs maximum of:Q173.
Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location (0100)_{16} and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is (016E)_{16}. The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word = 2 bytes). The CALL instruction is implemented as follows: Store the current value of PC in the stack Store the value of PSW register in the stack Load the starting address of the subroutine in PC The content of PC just before the fetch of a CALL instruction is (5FA0)_{16}. After execution of the CALL instruction, the value of the stack pointer isQ174.
Consider the following sequence of micro-operations. MBR \leftarrow PC MAR \leftarrow X PC \leftarrow Y Memory \leftarrow MBR Which one of the following is a possible operation performed by this sequence?Q177.
A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2's complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will beQ178.
How many number of times the instruction sequence below will loop before coming out of the loop? MOV AL, 00H A1: INC AL JNZ A1Q179.
A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________.Q180.
Assume that 16-bit CPU is trying to access a double word stating at an odd address. How many memory operations are required to access the data?