Digital Logic


Q41.

Consider the minterm list form of a Boolean function F given below. F(P,Q,R,S)=\sum m(0,2,5,7,9,11)+d(3,8,10,12,14) Here, m denotes a minterm and d denotes a don't care term. The number of essential prime implicants of the function F is ______.
GateOverflow

Q42.

Consider the Karnaugh map given below, where x represents "don't care" and blank represents 0. Assume for all inputs (a, b, c, d) the respective complements (\bar{a},\bar{b},\bar{c},\bar{d}) are also available. The above logic is implemented 2-input NOR gates only. The minimum number of gates required is ____________.
GateOverflow

Q43.

Let \bigoplus and \bigodot denote the Exclusive OR and Exclusive NOR operations, respectively. Which one of the following is NOT CORRECT?
GateOverflow

Q44.

What is the minimum number of two-input NAND gates used to perform the function of two-input OR gate?
GateOverflow

Q45.

Given f(w,x,y,z) = \sum_{m} (0,1,2,3,7,8,10) + \sum_{d} (5,6,11,15), where d represents the don't care condition in Karnaugh maps. Which of the following is a minimum product-of-sums (POS) form of f(w,x,y,z) ?
GateOverflow

Q46.

Consider the following gate networkWhich one of the following gates is redundant?
GateOverflow

Q47.

If w, x, y, z are Boolean variables, then which one of the following is INCORRECT ?
GateOverflow

Q48.

The 2-input XOR has a high output only when the input values are
GateOverflow

Q49.

In the diagram above, the inverter (NOT gate) and the AND-gates labeled 1 and 2 have delays of 9, 10 and 12 nanoseconds (ns), respectively. Wire delays are negligible. For certain values a and c, together with certain transition of b, a glitch (spurious output) is generated for a short time, after which the output assumes its correct value. The duration of glitch is:
GateOverflow

Q50.

The simplified SOP (Sum of Product) from the Boolean expression(P + \bar{Q} + \bar{R}) . (P + {Q} + R) . (P + Q +\bar{R})is
GateOverflow