GATE PYQ

Digital Logic

Q81.
A 4-bit carry look ahead Combinational Circuit, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the Combinational Circuit? Assume that the carry network has been implemented using two-level AND-OR logic.

Q82.
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed?

Q83.
Consider the ALU shown below If the operands are in 2's complement representation, which of the following operations can be performed by suitably setting the control lines K and C0 only (+ and - denote addition and subtraction respectively)?

Q84.
Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is

Q85.
Consider the following circuit composed of XOR gates and non-inverting buffers The non-inverting buffers have delays \delta _{1}= 2ns and \delta _{2}= 4ns as shown in the figure. Both XOR gates and al wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0. If the following waveform is applied at input. A, how many transition (s) (change of logic levels) occur (s) at B during the interval from 0 to 10 ns?

Q86.
Consider the following multiplexor where I0,I1,I2,I3 are four data input lines selected by two address line combinations A1A0 = 00,01,10,11 respectively and f is the output of the multiplexor. EN is the Enable input. The function f (x,y,z) implemented by the above circuit is

Q87.
The number of full and half-adders required to add 16-bit numbers is

Q88.
A multiplexer with a 4-bit data select input is a

Q89.
An N-bit carry lookahead adder, where N is a multiple of 4, employs ICs 74181 (4 bit ALU) and 74182 ( 4 bit carry lookahead generator). The minimum addition time using the best architecture for this adder is

Q90.
Consider the circuit in below figure which has a four bit binary number b_3b_2b_1b_0 as input and a five bit binary number, d_4d_3d_2d_1d_0 as output.