GATE CSE 2005
Q51.
Consider the following circuit involving a positive edge triggered D FF. Consider the following timing diagram. Let Ai represent the logic level on the line A in the i-th clock period. Let A' represent the complement of A. The correct output sequence on Y over the clock periods 1 through 5 isQ52.
Consider the following circuit. The flip-flops are positive edge triggered D FFs. Each state is designated as a two-bit string Q0Q1 . Let the initial state be 00. the state transition sequence is