Machine Instruction
Q11.
A non-pipelined CPU has 12 general purpose registers?(R0,R1,R2,...,R12). Following operations are supportedADD Ra, Rb, Rr Add Ra to Rb and store the result in RrMUL Ra, Rb, Rr Multiply Ra to Rb and store the result in RrMUL operation takes two clock cycles, ADD takes one clock cycle.Calculate minimum number of clock cycles required to compute the value of the expression XY+XYZ+YZ. The variable X,Y,Z are initially available in registers R0,R1 and R2 and contents of these registers must not be modified.Q12.
In X=(M+NxO)/(PxQ), how many one-address instructions are required to evaluate it?Q13.
Consider the following data path diagram. Consider an instruction: R0\leftarrow R1+R2. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively. 1. \; R2_r,TEMP1_r,ALU_{add},TEMP2_w 2. \; R1_r,TEMP1_w 3. \; PC_r,MAR_w,MEM_r 4. \; TEMP2_r,R0_w 5. \; MDR_r,IR_w Which one of the following is the correct order of execution of the above steps?Q14.
A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand field is _______ .Q15.
A byte addressable computer has a memory capacity of 2^{m} K B(k \text { bytes }) and can perform 2^{n} operations. An instruction involving 3 operands and one operator needs maximum of:Q16.
Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location (0100)_{16} and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is (016E)_{16}. The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word = 2 bytes). The CALL instruction is implemented as follows: Store the current value of PC in the stack Store the value of PSW register in the stack Load the starting address of the subroutine in PC The content of PC just before the fetch of a CALL instruction is (5FA0)_{16}. After execution of the CALL instruction, the value of the stack pointer isQ17.
Consider the following sequence of micro-operations. MBR \leftarrow PC MAR \leftarrow X PC \leftarrow Y Memory \leftarrow MBR Which one of the following is a possible operation performed by this sequence?Q20.
A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2's complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be