Sequential Circuit


Q21.

Consider a 3-bit counter, designed using T flip-flops, as shown below: Assuming the initial state of the counter given by PQR as 000, what are the next three states?
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Q22.

A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J=K=1 is the toggle mode and J=K=0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.
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Q23.

What are the final values of Q1 and Q0 after 4 clock cycles, if initial values are 00 in the sequential circuit shown below:
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Q24.

In a three stage counter, using RS flip flops what will be the value of the counter after giving 9 pulses to its input ? Assume that the value of counter before giving any pulses is 1 :
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Q25.

Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is
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Q26.

The above synchronous sequential circuit built using JK flip-flops is initialized with Q_{2}Q_{1}Q_{0} = 000. The state sequence for this circuit for the next 3 clock cycles is
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Q27.

Let k = 2^{n} . A circuit is built by giving the output of an n-bit binary counter as input to an n-to-2^{n} bit decoder. This circuit is equivalent to a
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Q28.

In an RS flip-flop, if the S line (Set line) is set high (1) and the R line (Reset line) is set low (0), then the state of the flip-flop is :
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Q29.

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. If all the flip-flops were reset to 0 at power on, what is the total number of distinct outputs (states) represented by PQR generated by the counter?
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Q30.

The minimum number of D flip-flops needed to design a mod-258 counter is
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