Interrupt
Q1.
A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and consumes 100 \mu s (micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an additional 200 \mu s to process the keystroke. Let T_1 denote the fraction of a second spent in polling and processing a keystroke. In an alternative implementation, the system uses interrupts instead of polling. An interrupt is raised for every keystroke. It takes a total of 1 ms for servicing an interrupt and processing a keystroke. Let T_2 denote the fraction of a second spent in servicing the interrupt and processing a keystroke. The ratio \frac{T_1}{T_2} is ______ . (Rounded off to one decimal place)Q5.
A computer handles several interrupt sources of which the following are relevant for this question. Interrupt from CPU temperature sensor (raises interrupt if CPU temperature is too high) Interrupt from Mouse (raises Interrupt if the mouse is moved or a button is pressed) Interrupt from Keyboard (raises Interrupt if a key is pressed or released) Interrupt from Hard Disk (raises Interrupt when a disk read is completed)Which one of these will be handled at the HIGHEST priority?Q6.
The following are some events that occur after a device controller issues an interrupt while process L is under execution. (P) The processor pushes the process status of L onto the control stack. (Q) The processor finishes the execution of the current instruction. (R) The processor executes the interrupt service routine. (S) The processor pops the process status of L from the control stack. (T) The processor loads the new PC value based on the interrupt. Which one of the following is the correct order in which the events above occur?Q8.
Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: The TRAP interrupts mechanism of the 8085 microprocessor:Q9.
A certain microprocessor requires 4.5 microseconds to respond to an interrupt. Assuming that the three interruptsI_1, I_2 and I_3 require the following execution time after the interrupt is recognized: I. I_1 requires 25 microseconds II. I_2 requires 35 microseconds III. I_3 requires 20 microseconds I_1 has the highest priority and I_3 has the lowest. What is the possible range of time for I_3 to be executed assuming that it may or may not occur simultaneously with other interrupts?