Interrupt


Q11.

The TRAP is one of the interrupts available in INTEL 8085. Which one of the following statements is true of TRAP ?
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Q12.

Which of the following devices should get higher priority in assigning interrupts?
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Q13.

Which of the following statements about synchronous and asynchronous I/O is NOT true?
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Q14.

A computer handles several interrupt sources of which the following are relevant for this question. Interrupt from CPU temperature sensor (raises interrupt if CPU temperature is too high) Interrupt from Mouse (raises Interrupt if the mouse is moved or a button is pressed) Interrupt from Keyboard (raises Interrupt if a key is pressed or released) Interrupt from Hard Disk (raises Interrupt when a disk read is completed)Which one of these will be handled at the HIGHEST priority?
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Q15.

The following are some events that occur after a device controller issues an interrupt while process L is under execution. (P) The processor pushes the process status of L onto the control stack. (Q) The processor finishes the execution of the current instruction. (R) The processor executes the interrupt service routine. (S) The processor pops the process status of L from the control stack. (T) The processor loads the new PC value based on the interrupt. Which one of the following is the correct order in which the events above occur?
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Q16.

The 8085 microprocessor responds to the presence of an interrupt
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Q17.

A certain microprocessor requires 4.5 microseconds to respond to an interrupt. Assuming that the three interruptsI_1, I_2 and I_3 require the following execution time after the interrupt is recognized: I. I_1 requires 25 microseconds II. I_2 requires 35 microseconds III. I_3 requires 20 microseconds I_1 has the highest priority and I_3 has the lowest. What is the possible range of time for I_3 to be executed assuming that it may or may not occur simultaneously with other interrupts?
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Q18.

A CPU has two modes-privileged and non-privileged. In order to change the mode from privileged to non-privileged
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Q19.

A device employing INTR line for device interrupt puts the CALL instruction on the data bus while
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Q20.

On receiving an interrupt from an I/O device,the CPU
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